Yun-Chen Lo  

I am currently a visiting PhD student at Harvard University Computer Science, advised by Prof. David Brooks and Prof. Gu-Yeon Wei. I am also a PhD candidate at National Tsing Hua University EE, advised by Prof. Ren-Shuo Liu. I have general research interests in VLSI design and efficient AI systems.

I am the first author of several top conference papers, including MICRO, ICLR, DAC, ICCAD, and ESSCIRC. I am also the co-author of several papers of ISSCC and IEDM. In addition, I have leadership experience in TSMC chip tap-out.

I received my B.S. and M.S. in Electrical Engineering from National Tsing Hua University. I was fortunate to work with Prof. Chi-Chun Lee (Jeremy) and Prof. Tsung-Yi Ho.

Google Scholar  /  LinkedIn  /  GitHub

profile photo
            Email:
            yunchenlo@seas.harvard.edu
            yunchen.lo@gapp.nthu.edu.tw
Publications

(* indicates equal contribution)

ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory
Yun-Chen Lo, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Chih-Chen Yeh, Wen-Chien Ting and Ren-Shuo Liu
IEEE Transactions on Computers (TC), 2024 (to appear)
(Top Journal)

Bucket Getter: A Bucket-based Processing Engine for Low-bit Block Floating Point (BFP) DNNs
Yun-Chen Lo, Ren-Shuo Liu
IEEE/ACM International Symposium on Microarchitecture (MICRO), 2023
(Top Conference)

Block and Subword-Scaling Floating-Point (BSFP) : An Efficient Non-Uniform Quantization For Low Precision Inference
Yun-Chen Lo, Tse-Kuang Lee, Ren-Shuo Liu
International Conference on Learning Representations (ICLR), 2023
(Top Conference)

Bit-Serial Cache: Exploiting Input Bit Vector Repetition to Accelerate Bit-Serial Inference
Yun-Chen Lo, Ren-Shuo Liu
ACM/IEEE Design Automation Conference (DAC), 2023
(Top Conference)

Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture
Yun-Chen Lo, Ren-Shuo Liu
ACM/IEEE Design Automation Conference (DAC), 2023
(Top Conference)

ISSA: Input-Skippable, Set-Associative Computing-in-Memory (SA-CIM) Architecture for Neural Network Accelerators
Yun-Chen Lo, Chih-Chen Yeh, Jun-Shen Wu, Chia-Chun Wang, Yu-Chih Tsai, Wen-Chien Ting and Ren-Shuo Liu
IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2022
(Top Conference)

Interference-free Design Methodology for Paper-Based Digital Microfluidic Biochips
Yun-Chen Lo, Bing Li, Sooyong Park, Kwanwoo Shin, and Tsung-Yi Ho
Asia and South Pacific Design Automation Conference (ASP-DAC), 2021
(Major conference)

Physically Tightly Coupled, Logically Loosely coupled, Near-Memory BNN Accelerator (PTLL-BNN)
Yun-Chen Lo, Yu-Chun Kuo, Yun-Sheng Chang, Jian-Hao Huang, Ruen-Shen Wu, Wen-Chien Ting, Tai-Hsing Wen, and Ren-Shuo Liu
IEEE European Solid-state Devices and Circuits Conference (ESSCIRC), 2019
(Major conference)

AI Edge Devices Using Computing-In-Memory and Processing-In-Sensor: From System to Device
Tzu-Hsiang Hsu, Yen-Cheng Chiu, Wei-Chen Wei, Yun-Chen Lo, Chung-Chuan Lo, Ren-Shuo Liu, KeaTiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh
IEEE International Electron Devices Meeting (IEDM), 2019 (Invited Paper)
(Top Conference)

DrowsyNet: Convolutional Neural Networks with Runtime Power-Accuracy Tunability Using Inference-Stage Dropout
Ren-Shuo Liu, Yun-Chen Lo, Yuan-Chun Luo, Chih-Yu Shen, and Cheng-Ju Lee
International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2018

Honors and Awards
  • 2020 Master Thesis Award, IEEE Taipei Section
  • 2020 Master Thesis Award, Institute of Information & Computing Machinery (IICM)
  • 2020 Master Thesis Award, Taiwan Information Storage Association (TiSA)
  • 2020 Oustanding Chip Design Award (Digital/AI), Taiwan Semiconductor Research Institute (TSRI)
  • 2020 Young Fellow, IEEE/ACM Design Automation Conference (DAC)
  • 2019 Master Fellowship, Novatek Corp
  • 2019 The Phi Tau Phi Scholastic Honor Society of the Republic of China Membership
  • 2019 ACM Student Research Competition (SRC) at MICRO, Second Place Award
  • 2018 ACM Student Research Competition (SRC) at MICRO, Second Place Award
  • 2017 First Place Award, Meichu Hackthon
  • 2017 First Place Award, EE Student Project Competition at National Tsing Hua University
    		•
    Industry Experience
  • Graduate Research Intern, 2022 Summer, Qualcomm
    Propose two memory optimizations to save near 30% power on Course-grained Reconfigurable Architecture (CGRA)
  • Research Intern, 2017 Summer, eMemory
    Survey devices, circuit, and architectures for memristors
  • Student Partner, 2016, Microsoft
    Hold workshops to teach Azure and Power BI
    		•

    Last Update: Jan. 2023

    Website Template